Voltage Controlled Oscillators(VCO) find usage in many circuits including Phase Locked Loop(PLL) and Delay Locked Loop(DLL) systems, where the VCO generates output frequencies depending on an input bias voltage to it. PLLs and DLLs are closed loop systems with feedback that employ voltage controlled elements and methods to generate reference frequencies for the loop to lock. VCOs can be implemented in many different known architectures such as LC tanks, Voltage bias controlled Inverter delay chains etc. Though the PLL is a different architecture than a DLL, they both use an Analog control voltage to control the VCO explained as follows.
In PLLs, based on feedback of how much the phase and/or frequency of a reference input signal is off from a derivative of VCO generated frequency, the VCO's bias voltage automatically moves in a direction so as to gradually increase/decrease the VCO's frequency for the loop to lock. Alternatively, in DLLs, based on feedback of how much the delay (hence phase) of a delayed signal from a reference input signal is off, the bias voltage controlling the delay of the inverters automatically moves in a direction so as to gradually increase/decrease the delay equal to an exact 1 period shift (or 360 degree phase shift). Both the PLLs and DLLs employ a phase detector that compares the reference input signal to the VCO derivative signal/inverter delayed signal generating increment or decrement pulses that in-turn increase or decrease a certain analog control voltage maintained by a charge pump, which is then fed back to the VCO/Delay inverters.
In an integrated circuit, a PLL or DLL circuit can be used to generate internal reference clock signals, their frequency divisions, precise phase shifts of one signal based on the frequency of the other etc. Because of process variations in an integrated circuit, and the Application's temperature and supply voltage variations, a VCO in an integrated circuit may require several frequency bands from which its operating frequency is selected. Consequently, a VCO may be provided that has a fixed set of frequency bands from which to choose at the initial start up of the PLL circuit (e.g., during the power-up sequence). However, when the VCO is operating, power supply voltage variations and temperature variations over time may affect the VCO frequency. For example, if the capacitance of an LC tank VCO changes with temperature or supply voltage or both, or if the Delay of inverter chain VCO changes with temperature or supply voltage or both, the PLL/DLL circuit has no mechanism for automatically adjusting its frequency band during operation and, consequently, the PLL/DLL circuit may lose its lock status and operate inefficiently possibly providing incorrect output frequencies, which is not acceptable.
A frequency band corresponds to a range of VCO output frequencies from a minimum to a maximum that is achieved by sweeping its control voltage in operational limits, covering all possible process, supply voltage and temperature conditions, and other specifications if any. Multiple frequency bands correspond to different bands provided by the same VCO when its architecture/operation is configured differently under the same above mentioned PVT and other specifications range. For continuity in frequencies covered by any two adjacent bands, there should be an overlap of frequencies. Configuring the VCO differently to fall in different bands can be linked to digital tune bits that can be externally controlled. This invention is targeted for automated band switching that involves internal automated real time tune bit transitions to change bands.
Currently known methods for automated band switching mechanisms include: band jumping from a higher band to the next lower band and so on; band jumping from a lower band to the next higher band and so on; intermingled band jumping. All of the art retains the control voltage while the band is switched. A different VCO frequency (or delay) occurs at the new band for each of the same control voltages. This could be a problem in certain situations where the control voltage in the new band is outside that band's operational limit.
One such situation is described in FIG. 4A, which is a graph of VCO frequency vs. VCO control voltage. FIG. 4B shows five problem waveforms. Referring to the graph in FIG. 4A, Let OPA be the current operating point in higher band HB. Assuming a temperature or voltage supply drift, or lowering of input frequency to PLL/DLL system tends to make OPA drift lower down the band to OPB. The VCO control voltage is at HB0. If delay 1/f2 is not slow enough for a lock in the PLL/DLL system, then the system requires a band switch to a lower frequency band. When a switch from HB to a lower frequency band LB is made from operating point OPB to OPC, the VCO's control voltage HB0 stays the same while the internal tune bits automatically change. If the delay (inverse of new VCO frequency: 1/f3) produced at the new control point is greater than 2× the input clock period fin, this causes the phase detector to malfunction by skipping one or more reference edges. This could happen if the frequency range covered by 2 bands is very large. The waveforms in FIG. 4B have voltage (y axis) vs. time (x axis) representation, the first waveform is a reference clock with a frequency fin to the DLL. The second waveform is the VCO generated clock that is the delayed version of first waveform. The aim of the VCO is to shift each pulse of the reference clock by 1 period (360 degree phase shift), eg, 1st pulse of reference clock to dotted pulse of VCO clock. So the 2nd rising edge of reference clock aligns with the dotted VCO clock pulse's rising edge for DLL to lock. The dashed-line pulse shown represents operating point OPB and is the reference's first pulse shifted by delay of 1/f2. The solid first pulse of the VCO clock is the reference clock delayed by 1/f3, represents the operating point OPc. The third waveform is a phase detector generated increment pulse that goes to the loop-controlling charge pump of the DLL. The solid-lined first increment pulse is an indication to move the first solid pulse of VCO clock towards the 3rd rising edge of the reference clock (which is a 720 degree phase shift) and is incorrectly locked. The correct increment pulse would be represented as the dashed pulse. So if a strobe signal is shifted by 90 degrees of reference clock in a locked DLL system, and if waveform 5 indicates the delayed strobe signal, then the dashed strobe signal is the correct output, but the DLL system shifts it incorrectly shown by the solid strobe signal, with an extra 360 degree phase of reference clock.
One embodiment describes methods and structures for the automated tuning of wide range frequency/delay VCOs used in wide range frequency PLLs and wide range delay DLLs, the large range accomplished with the use of multiple frequency or delay tuning bands, the automation utilizing a reset function that is invoked during band switching. This advance in structure is particularly needed in VCOs that have very wide delay tuning ranges using the analog tuning voltage within each individual tuning band. Presence of very large steps between the tuning ranges or bands even after sufficient overlap between the bands is possible. When large band switching steps (or coarse digital tuning) toward larger delays (smaller frequencies) are allowed, it makes possible a hazard of locking to an integer multiple greater than one of the desired delay increment/frequency decrement. The embodiments describe methods and structures to automatically switch bands with appropriate internal reset mechanisms, to a higher or a lower band depending on the current value of the VCO's control voltage, that could have moved and reached the end limit of the current band due to variations including supply voltage/temperature drifts or reference input frequency changes to the PLL/DLL system over time.